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| TH71221 27 to 930MHz FSK/FM/ASK Transceiver Features ! Single chip solution with only a few external components ! Stand-alone fixed-frequency user mode ! Programmable multi-channel user mode ! Low current consumption in active mode and very low standby current ! PLL-stabilized RF VCO (LO) with internal varactor diode ! Lock detect output in programmable user mode ! On-chip AFC for extended input frequency acceptance range ! 3wire bus serial control interface ! FSK/ASK mode selection ! FSK for digital data or FM for analog signal reception ! RSSI output for signal strength indication and ASK reception ! Peak detector for ASK detection ! Switchable LNA gain for improved dynamic range ! Automatic PA turn-on after PLL lock ! ASK modulation achieved by PA on/off keying ! 32-pin Quad Flat Lead Package (QFN) Ordering Information Part Number TH71221 Temperature Code E (-40 C to 85 C) Package Code LQ (32 L QFN 5x5 Quad) Delivery Form 73 pc/tube 5000 pc/T&R Application Examples ! General bi-directional half duplex digital data RF signaling or analog signal communication ! Tire Pressure Monitoring Systems (TPMS) ! Remote Keyless Entry (RKE) ! Low-power telemetry systems ! Alarm and security systems ! Wireless access control ! Garage door openers ! Networking solutions ! Active RFID tags ! Remote controls ! Home and building automation Pin Description top OUT_MIX VEE_IF IN_MIX GAIN_LNA OUT_LNA VEE_LNA IN_LNA OUT_PA bottom IN_IFA VCC_IF IN_DEM INT2/PDO INT1 OUT_DEM RSSI OUT_DTA TH71221 VEE_RO RO FSK_SW IN_DTA ASK/FSK VCC_DIG RE/SCLK LF VEE_PLL TNK_LO VCC_PLL FS1/LD VEE_DIG FS0/SDEN General Description The TH71221 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multichannel programmable or single-channel stand-alone, half-duplex data transmission systems. It can be used for applications in automotive, industrial-scientific-medical (ISM), short range devices (SRD) or similar applications operating in the frequency range of 300 MHz to 930 MHz. In programmable user mode, the transceiver can operate down to 27 MHz by employing an external VCO varactor diode. 39010 071221 Rev. 005 Page 1 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver Document Content 1 Theory of Operation ...................................................................................................4 1.1 1.2 1.3 1.4 1.5 General............................................................................................................................. 4 Technical Data Overview.................................................................................................. 4 Note on ASK Operation .................................................................................................... 4 Block Diagram .................................................................................................................. 5 User Mode Features ......................................................................................................... 5 2 3 Pin Definitions and Descriptions ..............................................................................6 Functional Description ............................................................................................10 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 PLL Frequency Synthesizer ........................................................................................... 10 Reference Oscillator (XOSC)..................................................................................................... 11 Reference Divider ...................................................................................................................... 11 Feedback Divider ....................................................................................................................... 11 Frequency Resolution and Operating Frequency ...................................................................... 11 Phase-Frequency Detector ........................................................................................................ 12 Lock Detector............................................................................................................................. 12 Voltage Controlled Oscillator with external Loop Filter.............................................................. 13 Loop Filter .................................................................................................................................. 13 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 Receiver Part.................................................................................................................. 13 LNA ............................................................................................................................................ 14 Mixer .......................................................................................................................................... 14 IF Amplifier ................................................................................................................................. 14 ASK Demodulator ...................................................................................................................... 14 FSK Demodulator ...................................................................................................................... 15 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 Transmitter Part .............................................................................................................. 15 Power Amplifier.......................................................................................................................... 15 Output Power Adjustment .......................................................................................................... 16 Modulation Schemes ................................................................................................................. 16 ASK Modulation ......................................................................................................................... 16 FSK Modulation ......................................................................................................................... 17 Crystal Tuning............................................................................................................................ 17 4 Description of User Modes......................................................................................18 4.1 4.1.1 4.1.2 4.1.3 4.1.4 Stand-alone User Mode Operation ................................................................................. 18 Frequency Selection .................................................................................................................. 18 Operation Mode ......................................................................................................................... 18 Modulation Type ........................................................................................................................ 19 LNA Gain Mode ......................................................................................................................... 19 4.2 4.2.1 Programmable User Mode Operation............................................................................. 19 Serial Control Interface Description ........................................................................................... 19 5 Register Description ................................................................................................20 5.1 Register Overview .......................................................................................................... 21 Page 2 of 44 Data Sheet June/07 39010 071221 Rev. 005 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Default Register Settings for FS0, FS1...................................................................................... 21 A - word ..................................................................................................................................... 22 B - word ..................................................................................................................................... 23 C - word..................................................................................................................................... 24 D - word..................................................................................................................................... 25 6 Technical Data..........................................................................................................26 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Absolute Maximum Ratings ............................................................................................ 26 Normal Operating Conditions ......................................................................................... 26 DC Characteristics.......................................................................................................... 27 PLL Synthesizer Timings ................................................................................................ 29 AC Characteristics of the Receiver Part ......................................................................... 29 AC Characteristics of the Transmitter Part ..................................................................... 30 Serial Control Interface................................................................................................... 30 Crystal Parameters ......................................................................................................... 30 7 Application Circuit Examples..................................................................................31 7.1 7.2 7.3 7.4 7.5 7.6 7.7 FSK Application Circuit Programmable User Mode (internal AFC option)...................... 31 FSK Application Circuit Stand-alone User Mode ............................................................ 32 FSK Test Circuit Component List (Fig. 14 and Fig. 15) .................................................. 33 ASK Application Circuit Programmable User Mode (normal data slicer option) ............. 34 ASK Test Circuit Component List (Fig. 16)..................................................................... 35 ASK Application Circuit Programmable User Mode (peak detector option).................... 36 ASK Test Circuit Component List (Fig. 17)..................................................................... 37 8 Extended Frequency Range ....................................................................................38 8.1 Board Component List (Fig. 18) ..................................................................................... 38 9 TX/RX Combining Network......................................................................................39 9.1 9.2 9.3 Board Component List (Fig. 19) ..................................................................................... 39 Typical LNA S-Parameters in Receive Mode ................................................................. 39 LNA Input Impedances in Transmit Mode ...................................................................... 40 10 Package Description ................................................................................................41 Soldering Information ..................................................................................................... 41 10.1 11 12 13 Reliability Information..............................................................................................42 ESD Precautions ......................................................................................................42 Disclaimer .................................................................................................................44 39010 071221 Rev. 005 Page 3 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 1 1.1 Theory of Operation General The main building block of the transceiver is a programmable PLL frequency synthesizer that is based on an integer-N topology. The PLL is used for generating the carrier frequency during transmission and for generating the LO signal during reception. The carrier frequency can be FSK-modulated either by pulling the crystal or by modulating the VCO directly. ASK modulation is done by on/off keying of the power amplifier. The receiver is based on the principle of a single conversion superhet. Therefore the VCO frequency has to be changed between transmit and receive mode. In receive mode, the default LO injection type is low-side injection. The TH71221 transceiver IC consists of the following building blocks: " " " " " " " Low-noise amplifier (LNA) for high-sensitivity RF signal reception with switchable gain Mixer (MIX) for RF-to-IF down-conversion IF amplifier (IFA) to amplify and limit the IF signal and for RSSI generation Phase-coincidence FSK demodulator with external ceramic discriminator or LC tank Operational amplifier (OA1), connected to demodulator output Operational amplifier (OA2), for general use Peak detector (PKDET) for ASK detection " " " " " " " " Control logic with 3wire bus serial control interface (SCI) Reference oscillator (RO) with external crystal Reference divider (R counter) Programmable divider (N/A counter) Phase-frequency detector (PFD) Charge pump (CP) Voltage controlled oscillator (VCO) with internal varactor Power amplifier (PA) with adjustable output power 1.2 Technical Data Overview ! Sensitivity: -107 dBm at ASK with 180 kHz IF filter BW ! Max. data rate with crystal pulling: 20 kbps NRZ ! Max. data rate with direct VCO modulation: 115 kbps NRZ ! Max. input level: -10 dBm at FSK and -20 dBm at ASK ! Input frequency acceptance: 10 to 150 kHz (depending on FSK deviation) ! FM/FSK deviation range: 2.5 to 80 kHz ! Analog modulation frequency: max. 10 kHz ! Crystal reference frequency: 3 MHz to 12 MHz ! External reference frequency: 1 MHz to 16 MHz ! Frequency range: 300 MHz to 930 MHz in programmable user mode ! Extended frequency range with external VCO varactor diode: 27 MHz to 930 MHz ! 315 MHz, 433 MHz, 868 MHz or 915 MHz fixedfrequency settings in stand-alone mode ! Power supply range: 2.2 V to 5.5 V ! Temperature range: -40 C to +85 C ! Standby current: 50 nA ! Operating current in receive: 6.5 mA (low gain) ! Operating current in transmit: 12 mA (at -2 dBm) ! Adjustable RF power range: -20 dBm to +10dBm ! Sensitivity: -105 dBm at FSK with 180 kHz IF filter BW 1.3 Note on ASK Operation Optimum ASK performance can be achieved by using an 8-MHz crystal for operation at 315 MHz, 434 MHz and 915 MHz. For details please refer to the software settings shown in sections 7.4 and 7.6. FSK operation is the preferred choice for applications in the European 868MHz band. 39010 071221 Rev. 005 Page 4 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 1.4 Block Diagram GAIN_LNA OUT_LNA VEE_LNA IN_MIX VEE_IF OUT_MIX VCC_IF IN_IFA RSSI 27 29 28 30 32 31 1 2 7 3 IN_DEM 6 OUT_DEM PKDET SW1 1.5pF bias OA2 4 FSK Demodulator MIX SW2 200k INT2/PDO 5 IN_LNA 26 MIX LNA LO IF INT1 IFA OA1 8 OUT_DTA Control Logic ASK SCI SDEN SDTA SCLK N counter VCO R counter RO RO FSK_SW FSK FS0/SDEN OUT_PA 25 PA ASK/FSK RE/SCLK VEE_RO 24 PS_PA 21 TNK_LO 20 VCC_PLL 23 LF 22 VEE_PLL 10 RO FS1/LD 11 19 9 12 13 15 16 17 18 14 Fig. 1: TH71221 block diagram 1.5 User Mode Features The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to Standalone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC in order to set the desired frequency of operation. There are 4 pre-defined frequency settings: 315MHz, 433.92MHz, 868.3MHz and 915MHz. The logic level at pin FS0/SDEN must not be changed after power up in order to remain in fixed-frequency mode. After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode (PUM). In this mode, the user can set any PLL frequency or mode of operation by the SCI. In SUM pins FS0/SDEN and FS1/LD are used to set the desired frequency, while in PUM pin FS0/SDEN is part of the 3-wire serial control interface (SCI) and pin FS1/LD is the look detector output signal of the PLL synthesizer. A mode control logic allows several operating modes. In addition to standby, transmit and receive mode, two idle modes can be selected to run either the reference oscillator only or the whole PLL synthesizer. The PLL settings for the PLL idle mode are taken over from the last operating mode which can be either receive or transmit mode. The different operating modes can be set in SUM and PUM as well. In SUM the user can program the transceiver via control pins RE/SCLK and TE/SDTA. In PUM the register bits OPMODE are used to select the modes of operation while pins RE/SCLK and TE/SDTA are part of the SCI. 39010 071221 Rev. 005 Page 5 of 44 Data Sheet June/07 VCC_DIG VEE_DIG TE/SDTA IN_DTA TH71221 27 to 930MHz FSK/FM/ASK Transceiver 2 1 Pin Definitions and Descriptions Name IN_IFA I/O Type input IN_IFA 1 140A VEE VEE Pin No. Functional Schematic VCC 2.2k 50 VCC Description IF amplifier input, approx. 2 k single-ended 2 VCC_IF supply positive supply of LNA, MIX, IFA, FSK Demodulator, PA, OA1 and OA2 VCC 90k VCC 3 IN_DEM analog I/O IN_DEM 3 60k IF amplifier output and demodulator input, connection to external ceramic discriminator or LC tank 1.5p 10A VEE 100A VEE 4 INT2/PDO output INT2/PDO 4 VCC OA2 output or peak detector output, high impedance in transmit and idle mode VEE 5 INT1 input VCC 200k + VCC inverting inputs of OA1 and OA2 120 OA1 5 120 INT1 OUT_DEM VEE 550k VCC 120 6 OUT_DEM analog I/O bias 6 demodulator output and non-inverting OA1 input, high impedance in transmit and idle mode 1k 550k OA2 10p VEE 10p 7 RSSI output VCC VCC 5A RSSI output, approx. 33 k RSSI 7 120 5A VEE VEE 39010 071221 Rev. 005 Page 6 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver Pin No. 8 Name OUT_DTA I/O Type output Functional Schematic VCC Description OA1 output, high impedance in transmit and idle mode OUT_DTA 8 VEE 9 10 VEE_RO RO ground analog I/O RO 10 VCC 2.6A 36p 36p ground of RO RO input, base of bipolar transistor 39k VEE 11 FSK_SW analog I/O FSK_SW 11 VCC FSK pulling pin, switch to ground or OPEN The switch is open in receive and idle mode VEE 12 IN_DTA input IN_DTA 12 VCC 120 ASK/FSK modulation data input, pull down resistor 120k 120k VEE 13 ASK/FSK input ASK/FSK 13 VCC ASK/FSK mode select input 120 VEE 14 15 VCC_DIG RE/SCLK supply input RE/SCLK 15 120k VEE VCC positive supply of serial port and control logic receiver enable input / clock input for the shift register, pull down resistor 120k 120 16 TE/SDTA input TE/SDTA 16 VCC 120 transmitter enable input / serial data input, pull down resistor 120k 120k VEE 39010 071221 Rev. 005 Page 7 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver Pin No. 17 Name FS0/SDEN I/O Type input Functional Schematic VCC Description frequency select input / serial data enable input FS0/SDEN 17 VEE 120 18 19 VEE_DIG FS1/LD ground input / output FS1/LD 19 120 VCC ground of serial port and control logic frequency select input / lock detector output VEE 20 VCC_PLL analog I/O TNK_LO 21 VCC VEE 6.3pF VD VCC_PLL 20 VEE VCO open-collector output, connection to VCC or external LC tank VCO open-collector output, connection to external LC tank charge pump output, connection to external loop filter 21 TNK_LO analog I/O LF 23 6.5k VCC VCOCUR 23 LF analog I/O 120 VEE VEE 22 24 VEE_PLL PS_PA ground analog I/O VCC 10A VCC ground of PLL frequency synthesizer power-setting input PS_PA 24 120 VEE VEE 25 OUT_PA output VCC OUT_PA 25 20p VEE VEE 1k power amplifier opencollector output 39010 071221 Rev. 005 Page 8 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver Pin No. 27 28 Name VEE_LNA OUT_LNA I/O Type ground output Functional Schematic OUT_LNA bias Description ground of LNA and PA 28 LNA open-collector output, connection to external LC tank at RF 37 3.8k VEE 26 IN_LNA input IN_LNA 26 VEE 0.8p VEE LNA input, single-ended 29 GAIN_LNA input GAIN_LNA 29 VEE VCC LNA gain control input 120 30 IN_MIX input IN_MIX 30 VCC 210 mixer input, approx. 200 single-ended LO bias VEE VEE 31 32 VEE_IF OUT_MIX ground output OUT_MIX 32 VEE VCC ground of IFA, Demodulator, OA1 and OA2 mixer output, approx. 330 single-ended 100 39010 071221 Rev. 005 Page 9 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 3 3.1 Functional Description PLL Frequency Synthesizer The TH71221 contains an integer-N PLL frequency synthesizer. A PLL circuit performs the frequency synthesis via a feedback mechanism. The output frequency fVCO is generated as an integer multiple of the phase detector comparison frequency fR .This reference frequency fR is generated by dividing the output frequency fRO of a crystal oscillator. The phase detector utilizes this signal as a reference to tune the VCO and in the locked state it must be equal to the desired output frequency, divided by the feedback divider ratio N. VCC Charge Pump Reference Oscillator f RO Reference Divider Phase-frequency Detector fR External Loop Filter LF Feedback Divider f VCO Voltage Controlled Oscillator fN Fig. 2: Integer-N PLL Frequency Synthesizer Topology The output frequency of the synthesizer fVCO can be selected by programming the feedback divider and the reference divider. The only constraint for the frequency output of the system is that the minimum frequency resolution, or the channel spacing, must be equal to the PFD frequency fR, which is given by the reference frequency fRO and the reference divider factor R: fR = f RO . R (1) When the PLL is unlocked (e.g. during power up or during reprogramming of a new feedback divider ratio N), the phase-frequency detector PFD and the charge pump create an error signal proportional to the phase difference of the two input signals. This error signal is low-pass filtered through the external loop filter and input to the VCO to control its frequency. A very low frequency resolution increases the settling time of the PLL and reduces the ability to cancel out VCO perturbations, because the loop filter is updated every 1/fR. After the PLL has locked, the VCO frequency is given by the following equation: f VCO = N f RO = N fR . R (2) There are four registers available to set the VCO frequencies in receive (registers RR and NR) and in transmit mode (registers RT and NT). These registers can be programmed using the Serial Control Interface in Programmable User Mode (PUM). In case of Stand-alone User Mode (SUM), the registers are set fixed values (refer to para. 4.1.1). The VCO frequency is equal to the carrier frequency in transmit mode. While in receive mode the VCO frequency is offset by the intermediate frequency IF. This is because of the super-heterodyne nature of the receive part. 39010 071221 Rev. 005 Page 10 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 3.1.1 Reference Oscillator (XOSC) The reference oscillator is based on a Colpitts topology with two integrated functional capacitors as shown in figure 3. The circuitry is optimized for a load capacitance range of 10 pF to 15 pF. The equivalent input capacitance CRO offered by the oscillator input pin RO is about 18pF. To ensure a fast and reliable start-up and a very stable frequency VCC over the specified supply voltage and temperature range, the IRO oscillator bias circuitry provides an amplitude regulation. The amplitude on pin RO is monitored in order to regulate the current of 36pF 36pF the oscillator core IRO. There are two limits ROMAX and ROMIN RO between the regulation is maintained. These values can be changed via serial control interface in Programmable User Mode XTAL (PUM). In Stand-alone User Mode (SUM), ROMAX and ROMIN are set to default values (refer to para. 5.1.3). ROMAX defines the CX2 VEE start-up current of the oscillator. The ROMIN value sets the desired steady-state current. If ROMIN is sufficient to achieve an FSKSW amplitude of about 400 mV on pin RO, the current IRO will be set CX1 to ROMIN. Otherwise the current will be permanently regulated between ROMIN and ROMAX. If ROMIN and ROMAX are equal, no regulation takes place. For most of the applications ROMIN and ROMAX should not be changed from default. Fig. 3: Reference oscillator circuit 3.1.2 Reference Divider The reference divider provides the input signal of the phase detector by dividing the signal of the reference oscillator. The range of the reference divider is 4 R 1023 . 3.1.3 Feedback Divider (3) The feedback divider of the PLL is based on a pulse-swallow topology. It contains a 4-bit swallow A-counter, a 13-bit program B-counter and a prescaler. The divider ratio of the prescaler is controlled by the program counter and the swallow counter. During one cycle, the prescaler divides by 17 until the swallow A-counter reaches its terminal count. Afterwards the prescaler divides by 16 until the program counter reaches its terminal count. Therefore the overall feedback divider ratio can be expressed as: N = 17 A + 16 (B - A) . (4) The A-counter configuration represents the lower bits in the feedback divider register (N0-3 = A0-3) and the upper bits the B-counter configuration (N4-16 = B0-12) respectively. According to that, the following counter ranges are implemented: 0 A 15 ; 4 B 8191 (5) and therefore the range of the overall feedback divider ratio results in: 64 N 131071 . (6) The user does not need to care about the A- and B-counter settings. It is only necessary to know the overall feedback divider ratio N to program the register settings. 3.1.4 Frequency Resolution and Operating Frequency It is obvious from (2) that, at a given frequency resolution fR, the maximum operating frequency of the VCO is limited by the maximum N-counter setting. The table below provides some illustrative numbers. Please also refer to section 4.4.1 for the pre-configured settings in Stand-alone User Mode (SUM). 39010 071221 Rev. 005 Page 11 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver Crystal frequency fRO 3.0000MHz 3.0000MHz 8.0000MHz 8.0000MHz 8.0000MHz Frequency resolution fR 2.93kHz 2.93kHz 12.5kHz 25kHz 250kHz R counter 1023 1023 640 320 32 N counter 13107 131071 35812 34746 3660 Operating frequency fVCO 38.437MHz 384.372MHz 447.65MHz 868.65MHz 915.0MHz 3.1.5 Phase-Frequency Detector The phase-frequency detector creates an error voltage proportional to the phase difference between the reference signal fR and fN. The implementation of the phase detector is a phase-frequency type. That circuitry is very useful because it decreases the acquisition time significantly. The gain of the phase detector can be expressed as: K PD = I CP , 2 (7) where ICP is the charge pump current which is set via register CPCUR. In the TH7122 design the VCO frequency control characteristic is with negative polarity. This means the VCO frequency increases if the loop filter output voltage decreases and vice versa. When an external varactor diode is added to the VCO tank, the tuning characteristic can be changed between positive and negative depending on the particular varactor diode circuitry. Therefore the PDFPOL register can be used to define the phase detector polarity. 3.1.6 Lock Detector In Programmable User Mode a lock-detect signal LD is available at pin FS1/LD (pin 19). The lock detection circuitry uses Up and Down signals from the phase detector to check them for phase coherency. Figure 4 shows an overview of the lock signal generation. The locked state and the unlock condition will be decided on the register settings of LDTM and ERTM respectively. In the start-up phase of the PLL, Up and Down signals are quite unbalanced and counter CNT_LD receives no clock signal. When the loop approaches steady state, the signals Up and Down begin to overlap and CNT_LD counts down. Herein register LDTM sets the number of counts which are necessary to set the lock detection signal LD. If an unlock condition occurs, the counter CNT_LD will be reloaded and therefore its CARRY falls back. LDTM [1 : 0] Up Down 2 D CR CARRY Control Logic RESET LD LOCKMODE & & PFD LOAD R S Q LD MUX CNT_LD = ERTM [1 : 0] FRO 2 D CARRY & CR LOAD RO Fig. 4: Lock Detection Circuit CNT_ER 39010 071221 Rev. 005 Page 12 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver The CNT_ER supervises the unlock condition. If Up and Down are consecutive, the counter CNT_ER will be reloaded permanently and its CARRY will not be set, otherwise the counter level of CNT_ER will be reduced by the reference oscillator clock (1/fRO). The register ERTM decides on the maximum number of clocks during Up and Down signals can be non-consecutive without loosing the locked state. The transceiver offers two ways of analyzing the locked state. If the register LOCKMODE is set to `0', only one occurrence of the locked state condition is needed to remain LD = 1 during the whole active mode, otherwise the state of the PLL will be observed permanently. 3.1.7 Voltage Controlled Oscillator with external Loop Filter VCC The transceiver provides a LC-based voltage-controlled oscillator with an external inductance element connected between VCC and pin TNK_LO. An internal varactor diode in series with a fixed capacitor forms the variable part of the oscillator tank. The oscillation frequency is adjusted by the DC-voltage at pin LF. The tuning sensitivity of the VCO is approximately 20MHz/V for 433MHz operations and 40MHz/V at 868MHz. Since the internal varactor is connected to VCC, a lower voltage on pin LF causes the capacitance to decrease and the VCO frequency to increase. For this reason the phase detector polarity should be negative (PFDPOL = 0). If the operation frequency is below 300MHz, an external varactor diode between pin TNK_LO and VCC_PLL is necessary. The corresponding application schematic is shown in section 8. The VCO current VCOCUR can be adjusted via serial control interface in order to ensure stable oscillations over the whole frequency range. For lowest LO emission in receive mode, VCOCUR should be set to the lowest value. Fig. 5: VCO schematic External Loop Filter TNK_LO 6.3pF LF VD VCC_PLL Charge Pump + VCOCUR VEE 3.1.8 Loop Filter RF CF1 Since the loop filter has a strong impact on the function of the PLL, it must be chosen carefully. For FSK operation the bandwidth of the loop filter must be selected wide enough for a fast relock of the PLL during crystal pulling. The bandwidth must of course also be larger than the data rate. In case of ASK or OOK the bandwidth should be extended even further to allow the PLL to cancel out VCO perturbations that might be caused by the PA on/off keying. The suggested filter topology is shown in Fig. 6. The dimensions of the loop filter elements can be derived using well known formulas in application notes and other reference literature. Fig. 6: 2nd order Loop filter VCC CF2 LF VCO + 3.2 Receiver Part The RF front-end of the receiver part is a super-heterodyne configuration that converts the input radiofrequency (RF) signal into an intermediate frequency (IF) signal. The most commonly used IF is 10.7 MHz, but IFs in the range of 0.4 to 22 MHz can also be used. According to the block diagram, the front-end consists of a LNA, a Mixer and an IF limiting amplifier with received signal strength indicator (RSSI). The local oscillator (LO) signal for the mixer is generated by the PLL frequency synthesizer. As the receiver constitutes a superhet architecture, there is no inherent suppression of the image frequency. It depends on the particular application and the system's environmental conditions whether an RF front-end filter should be added or not. If image rejection and/or good blocking immunity are relevant system parameters, a band-pass filter must be placed either in front or after the LNA. This filter can be a SAW (surface acoustic wave) or LC-based filter (e.g. helix type). 39010 071221 Rev. 005 Page 13 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 3.2.1 LNA The LNA is based on a cascode topology for low-noise, high gain and good reverse isolation. The open collector output has to be connected to an external resonance circuit which is tuned to the receive frequency. The gain of the LNA can be changed in order to achieve a high dynamic range. There are two possibilities for the gain setting which can be selected by the register bit LNACTRL. External control can be done via the pin GAIN_LNA, internal control is given by the register bit LNAGAIN. In case of external gain control, a hysteresis of about 340 mV can be chosen via the register bit LNAHYST. This configuration is useful if an automatic gain control loop via the RSSI signal is established. In transmit mode the LNA-input is shorted to protect the amplifier from saturation and damaging. 3.2.2 Mixer The mixer is a double-balanced mixer which down converts the receive frequency to the IF. The default LO injection type is low side (fVCO = fRX - fIF). But also high side injection is possible (fVCO = fRX + fIF). In this case, the data signals polarity is inverted due to the mixing process. To avoid this, the transmitted data stream can be inverted too by setting DTAPOL to `1'. The output impedance of the mixer is about 330 in order to match to an external IF filter. 3.2.3 IF Amplifier After passing the channel select filter which sets the IF bandwidth the signal is limited by means of an high gain limiting amplifier. The small signal gain is about 80 dB. The RSSI signal is generated within the IF amplifier. The output of the RSSI signal is available at pin RSSI. The voltage at this pin is proportional to the input power of the receiver in dBm. Using this RSSI output signal the signal strength of different transmitters can be distinguished. 3.2.4 ASK Demodulator * * standard ASK demodulation or ASK demodulation with peak detector. The receive part of the TH7122 allows for two ASK demodulation configurations: The default setting is standard ASK demodulation. In this mode SW1 and SW2 are closed and the RSSI output signal directly feeds the data slicer setup by means of OA1. The data slicer time constant equals to T = 200k C3 , (8) with C3 external to pin INT1. This time constant should be larger than the longest possible bit duration of the data stream. This is required to properly extract the ASK data's DC level. The purpose of the DC (or mean) level at the negative input of OA1 is to set an adaptive comparator threshold to perform the ASK detection. Alternatively a peak detector can be used to define the ASK detection threshold. In this configuration the peak detector PKDET is enabled, SW1 is closed and SW2 is open, and the peak detector output is multiplexed to pin INT2/PDO. This way the peak detector can feed the data slicer, again constituted by OA1 and a few external R and C components. The peak detection mode is selectable in programmable user mode. 39010 071221 Rev. 005 Page 14 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 3.2.5 FSK Demodulator The implemented FSK demodulator is based on the phase-coincidence principle. A discriminator tank, which can either consist of a ceramic discriminator or an LC tank, is connected to pin IN_DEM. If FSK mode is selected SW1 is open, SW2 is closed and the output of OA2 is multiplexed to pin INT2/PDO. The demodulator output signal directly feeds the data slicer setup by means of OA1. The data slicer time constant can be calculated using (8). This time constant should be larger than the longest possible bit duration of the data stream as described in the previous paragraph. An on-chip AFC circuit tolerates input frequency variations. The input frequency acceptance range is proportional to the FSK or FM deviation. It can be adjusted by the discriminator tank. The AFC feature is disabled by default and can be activated in programmable mode. 3.3 Transmitter Part The output of the PLL frequency synthesizer feeds a power amplifier (PA) in order to setup a complete RF transmitter. The VCO frequency is identical to the carrier frequency. 3.3.1 Power Amplifier The power amplifier (PA) has been designed to deliver about 10 dBm in the specified frequency bands. Its pin OUT_PA is an open collector output. The larger the output voltage swing can be made the better the power efficiency will be. The PA must be matched to deliver the best efficiency in terms of output power and current consumption. The collector must be biased to the positive supply. This is done by means of an inductor parallel tuned with a capacitor. Or it is made large enough in order not to affect the outVCC VCC put matching network. S-parameters of pin OUT_PA are not useful because the output is very high resistive with a small 3pF L RL portion of parallel capacitance. Since the open-collector output transistor can be considered as a current source, the only parameters needed to design the output matching netOUT_PA work are the output capacitance, the supply voltage VCC, the transistor's saturation voltage and the power delivered to the VEE load PO. In order to avoid saturation of the output stage, a saturation voltage VCESAT of about 0.7 V should be considered. The Fig. 7: OUT_PA schematic real part of the load impedance can then be calculated using RL = (VCC - VCE SAT ) 2 . 2 PO (9) The output capacitance is typically 3 pF. 39010 071221 Rev. 005 Page 15 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 3.3.2 Output Power Adjustment P4 20.00 P0 / dBm The maximum output power is adjustable via the external resistor RPS as shown in Figure 8. There are four predefined power settings in programmable user mode which can be set in the register TXPOWER. The maximum power setting P4 is the default setting. 10.00 0.00 315MHz 433MHz 868MHz 915MHz -10.00 -20.00 -30.00 Fig. 8: Output power vs. RPS -40.00 1 10 RPS / kOhm 100 3.3.3 Modulation Schemes The RF carrier generated by the PLL frequency synthesizer can be ASK or FSK modulated. Depending on the selected user mode, the modulation type can be selected either by the ASK/FSK pin or via the serial control interface. Data is applied to pin IN_DTA. The data signal can be inverted by the bit DTAPOL. The following tables for ASK and FSK modulation are valid for non-inverted data (DTAPOL = 0) 3.3.4 ASK Modulation Description Power amplifier is turned off Power amplifier is turned on (according to the selected output power) The transceiver is ASK-modulated by turning on and off the power amplifier. Please also refer to para. 1.3 for ASK modulation limits. IN_DTA 0 1 39010 071221 Rev. 005 Page 16 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 3.3.5 FSK Modulation * FSK modulation via crystal pulling VCC IRO 36pF 36pF FSK modulation can be achieved by pulling the crystal oscillator frequency. A CMOS-compatible data stream applied at pin IN_DTA digitally modulates the XOSC via an integrated NMOS switch. Two external pulling capacitors CX1 and CX2 allow the FSK deviation f and center frequency fc to be adjusted independently. At IN_DTA = LOW CX2 is connected in parallel to CX1 leading to the low-frequency component of the FSK spectrum (fmin); while at IN_DTA = HIGH CX2 is deactivated and the XOSC is set to its high frequency, leading to fmax. IN_DTA 0 1 Description fmin = fc - f (FSK switch is closed) fmax = fc + f (FSK switch is open) RO XTAL CX2 FSKSW VEE CX1 Fig. 9: Crystal Pulling Circuit An external reference signal can be directly AC-coupled to the reference oscillator input pin RO. Then the transceiver is used without a XTAL. Now the reference signal sets the carrier frequency and has to contain the FSK (or FM) modulation * FSK modulation via direct VCO modulation IN_DTA VCC CB6 17 FS0/SDEN 18 VEE_DIG Alternatively FSK or FM can be achieved by injecting the modulating signal into the loop filter to directly control the VCO frequency. Fig. 10 shows a circuit proposal for direct VCO modulation. This circuit is recommended for data rates in excess of about 20 kbps NRZ. An external VCO tuning varactor should be added for narrow-band applications, for example at channel spacings of 25 kHz. For details please refer to the application notes "TH7122 and TH71221 High Speed Data Communication" and "TH7122 and TH71221 Used In Narrow Band FSK Applications" as well as to the "TH7122 and TH71221 Cookbook" Fig. 10: Circuit schematic for direct VCO modulation CM1 RF CF2 L0 RM1 CF1 19 FS1/LD 20 VCC_PLL 21 TNK_LO 22 VEE_PLL 23 LF 24 3.3.6 Crystal Tuning f XTAL f max L1 C1 fo R1 C0 CL eff A crystal is tuned by the manufacturer to the requested oscillation frequency f0 for a certain load capacitance CL within the specified calibration tolerance. The only way to tune this oscillation frequency is to vary the effective load capacitance CLeff seen by the crystal. Figure 8 shows the oscillation frequency of a crystal in dependency on the effective load capacitance. This capacitance changes in accordance with the logic level of IN_DTA around the specified load capacitance. The figure illustrates the relationship between the external pulling capacitors and the frequency deviation. Fig. 11: Crystal Tuning Characteristic f min CX1 CRO CX1+CRO CL (CX1+CX2) CRO CX1+CX2+CRO CL eff 39010 071221 Rev. 005 Page 17 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 4 4.1 Description of User Modes Stand-alone User Mode Operation After power up the transceiver is set to stand-alone user mode. In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC to set the desired frequency of operation. The logic level at pin FS0/SDEN must not be changed after power up in order to remain in stand-alone user mode. The default settings of the control word bits in stand-alone user mode are described in the frequency selection table. Detailed information about the default settings can be found in the tables of section 5. 4.1.1 Frequency Selection Channel frequency 433.92 MHz 1 0 868.3 MHz 0 0 7.1505 MHz 32 223.45 kHz 1894 423.22 MHz 433.92 MHz 32 223.45 kHz 1942 433.92 MHz 433.92 MHz 10.7 MHz 16 446.91 kHz 1919 857.60 MHz 868.30 MHz 16 446.91 kHz 1943 868.30 MHz 868.30 MHz 10.7 MHz 18 397.25 kHz 766 304.30 MHz 315.00 MHz 18 397.25 kHz 793 315.00 MHz 315.00 MHz 10.7 MHz 32 223.45 kHz 4047 904.30 MHz 915.00 MHz 32 223.45 kHz 4095 915.00 MHz 915.00 MHz 10.7 MHz 315 MHz 1 1 915 MHz 0 1 FS0/SDEN FS1/LD Reference oscillator frequency R counter ratio in RX mode (RR) PFD frequency in RX mode N counter ratio in RX mode (NR) VCO frequency in RX mode RX frequency R counter ratio in TX mode (RT) PFD frequency in TX mode N counter ratio in TX mode (NT) VCO frequency in TX mode TX frequency IF in RX mode In stand-alone user mode, the transceiver can be set to Standby, Receive, Transmit or Idle mode (only PLL synthesizer active) via control pins RE/SCLK and TE/SDTA. The modulation scheme and the LNA gain are set by pins ASK/FSK and GAIN_LNA, respectively. 4.1.2 Operation Mode Operation mode RE/SCLK TE/SDTA Standby 0 0 Receive 1 0 Transmit 0 1 Idle 1 1 Note: Pins with internal pull-down 39010 071221 Rev. 005 Page 18 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 4.1.3 Modulation Type Modulation type ASK / FSK ASK 0 FSK 1 4.1.4 LNA Gain Mode LNA gain GAIN_LNA high 0 low 1 4.2 Programmable User Mode Operation The transceiver can also be used in programmable user mode. After power-up the first logic change at pin FS0/SDEN enters into this mode. Now full programmability can be achieved via the Serial Control Interface (SCI). 4.2.1 Serial Control Interface Description A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in programmable user mode. At each rising edge of the SCLK signal, the logic value on the SDTA pin is written into a 24-bit shift register. The data stored in the shift register are loaded into one of the 4 appropriate latches on the rising edge of SDEN. The control words are 24 bits lengths: 2 address bits and 22 data bits. The first two bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. The first incoming bit is the most significant bit (MSB). To program the transceiver in multi-channel application, four 24-bit words may be sent: A-word, B-word, C-word and D-word. If individual bits within a word have to be changed, then it is sufficient to program only the appropriate 24-bit word. The serial data input timing and the structure of the control words are illustrated in Fig. 12 and 13. 22 22 SDTA SCLK 24-BIT SHIFT REGISTER 2 A - LATCH B - LATCH C - LATCH D - LATCH 22 A-word 22 22 B-word 22 `00' `01' 22 C-word SDEN ADDR DECODER `10' `11' 22 22 D-word Fig. 12: SCI Block Diagram 39010 071221 Rev. 005 Page 19 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver Due to the static CMOS design, the SCI consumes virtually no current and it can be programmed in active as well as in standby mode. If the transceiver is set from standby mode to any of the active modes (idle, receive, transmit), the SCI settings remain the same as previously set in one of the active modes, unless new settings are done on the SCI while entering into an active mode. Invalid data SDTA Invalid data MSB bit 23 bit 22 bit 1 LSB bit 0 SCLK t CS t CH t CWL tCWH SDEN tES tEW tEH Fig. 13: Serial Data Input Timing 5 Register Description As shown in the previous section there are four control words which stipulate the operation of the whole chip. In Stand-alone User Mode SUM the intrinsic default values with respect to the applied levels at pins FS0 and FS1 lay down the configuration of the transceiver. In Programmable User Mode (PUM) the register settings can be changed via 3-wire interface SCI. The default settings which vary with the desired operating frequency depend on the voltage levels at the frequency selection pins FS0 and FS1 before entering the PUM. Table 5.1.1 shows the default register settings of different frequency selections. It should be noted that the channel frequency listed below will be achieved with a crystal frequency of 7.1505 MHz. The following table depicts an overview of the register configuration of the TH71221. 39010 071221 Rev. 005 Page 20 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 5.1 Register Overview DATA LSB 9 8 7 6 5 4 3 2 1 0 Bit No. default WORD MSB 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 DATAPOL 0 MODSEL 0 CPCUR 0 LOCKMODE 1 PACTRL 1 1 1 Set to 1 1 LNAGAIN 0 0 Depends on FS0/FS1 voltage level after power up TXPOWER [ 1 :0 ] OPMODE [1:0] A 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 1 0 PKDET 1 Set to 1 1 DELPLL 1 LNAHYST 0 0 1 1 ROMAX [2:0] 1 0 1 ROMIN [2:0] 0 9 8 7 6 5 RR [9:0] 4 3 IDLE 2 1 0 Bit No. default Depends on FS0/FS1 voltage level after power up B 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 0 0 LNACTRL 0 VCOCUR [ 1 :0 ] PFDPOL BAND 9 8 7 6 5 RT [9:0] 4 3 OA2 AFC 2 1 0 Bit No. default Depends on FS0/FS1 voltage level after power up C 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 1 0 MODCTRL 0 1 0 0 9 NR [ 16 : 0 ] 8 7 6 5 4 3 2 1 0 Bit No. default Depends on FS0/FS1 voltage level after power up D 5.1.1 FS1 0 0 1 1 Note: Default Register Settings for FS0, FS1 FS0 0 1 0 1 Channel frequency 868.30 MHz 433.92 MHz 915.00 MHz 315.00 MHz BAND 1 0 1 0 VCOCUR [1:0] 11 01 11 00 RR [9:0] 16d 32d 32d 18d NR [ 16 :0 ] 1919d 1894d 4047d 766d RT [ 9 :0 ] 16d 32d 32d 18d NT [ 16 : 0 ] 1943d 1942d 4095d 793d d - decimal code A detailed description of the registers function and their configuration can be found in the following sections. 39010 071221 Rev. 005 Page 21 of 44 NT [ 16 : 0 ] LDTM [ 1 :0 ] ERTM [ 1 :0 ] Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 5.1.2 A - word Name Bits [9:0] 4d .. 1023d Operation mode 00 01 10 11 0 1 Standby mode Receive mode Transmit mode Idle mode LNA gain low LNA gain high LNA gain set to `1' for correct function Output power steps 00 01 10 11 0 1 0 P1 P2 P3 P4 Set the PA-on condition PA is switched on if the PLL locks PA is always on in TX mode Set the PLL locked state observation mode before lock only #default Description Reference divider ratio in RX operation mode RR OPMODE [11:10] LNAGAIN not used [12] #default This selection is valid if bit LNACTR (bit 21 in C-word) is set to internal LNA gain control. [13] TXPOWER [15:14] #default PACTRL [16] #default #default LOCKMODE [17] 1 Locked state condition will be ascertained only one time afterwards the LD signal remains in high state. before and after lock locked state will be observed permanently Charge Pump output current CPCUR [18] 0 1 0 1 260 A 1300 A Modulation mode ASK FSK Input data polarity #default MODSEL [19] #default This selection is valid if bit MODCTRL (bit 21 in D-word) is set to internal modulation control. 0 normal `0' for space at ASK or fmin at FSK, `1' for mark at ASK or fmax at FSK #default DTAPOL [20] 1 inverse `1' for space at ASK or fmin at FSK, `0' for mark at ASK or fmax at FSK Active blocks in IDLE mode IDLESEL [21] 0 1 only RO active whole PLL active #default 39010 071221 Rev. 005 Page 22 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 5.1.3 B - word Name Bits [9:0] 4d .. 1023d Set the desired steady state current of the reference oscillator 000 001 010 011 100 101 110 111 0 A 75 A 150 A #default 225 A 300 A 375 A 450 A 525 A 0 A 75 A 150 A 225 A 300 A 375 A 450 A 525 A #default disabled enabled OA2 can be enabled in FSK receive mode. OA2 is disabled in ASK mode receive. The control circuitry regulates the current of the oscillator core between the values ROMAX and ROMIN. As the regulation input signal the amplitude on pin RO is used. If the ROMIN value is sufficient to achieve an amplitude of about 400mV on pin RO the current of the reference oscillator core will be set to ROMIN. Otherwise the current will be permanently regulated between ROMAX and ROMIN. If ROMIN and ROMAX are equal no regulation of the oscillator current occurs. Please also note the block description of the reference oscillator in para. 3.1.1 Description Reference divider ratio in TX operation mode RT ROMIN [12:10] Set the start-up current of the reference oscillator 000 001 010 011 100 101 110 111 ROMAX [15:13] Set the start-up current of the reference oscillator core. Please also note the description of the ROMIN register and the block description of the reference oscillator which can be seen above. OA2 operation OA2 [16] 0 1 #default Internal AFC feature AFC [17] 0 1 disabled enabled Hysteresis on pin GAIN_LNA #default LNAHYST [18] 0 1 0 disabled enabled Delayed start of the PLL undelayed start PLL starts at the reference oscillator start-up #default DELPLL [19] 1 starts after 8 valid RO-cycles #default PLL starts after 8 valid RO-cycles before entering an active mode to ensure reliable oscillation of the reference oscillator. not used [20] 0 disabled set to `1' for correct function RSSI Peak Detector #default PKDET [21] 1 The RSSI output signal directly feeds the data slicer setup by means of OA1. enabled In ASK receive mode the RSSI Peak Detector output is multiplexed to pin INT2/PDO. 39010 071221 Rev. 005 Page 23 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 5.1.4 C - word Name Bits [16:0] 64d .. 131071d 0 1 Set the desired frequency range recommended at fRF < 500 MHz recommended at fRF > 500MHz Some tail current sources are linked to this bit in order to save current for low frequency operations. Description Feedback divider ratio in RX operation mode NR BAND [17] VCO active current VCOCUR [19:18] 00 01 10 11 low current (300 A) standard current (500 A) high1 current (700 A) high2 current (900 A) Phase Detector polarity 0 PFDPOL [20] 1 negative #default positive VCO OUTPUT FREQUENCY pos neg VCO INPUT VOLTAGE 0 LNA gain control mode external LNA gain control LNA gain will be set via pin GAIN_LNA. #default LNACTRL [21] 1 internal LNA gain control LNA gain will be set via bit LNAGAIN (bit 12 in A-word). Nevertheless pin GAIN_LNA must be connected to either VCC or VEE. 39010 071221 Rev. 005 Page 24 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 5.1.5 D - word Name Bits [16:0] 64d .. 131071d 00 01 10 11 00 01 10 11 0 Set the unlock condition of the PLL 2 clocks #default Set the maximum allowed number of reference 4 clocks (1/fRO) during the phase detector output signals 8 clocks DOWN) can be in-consecutive. 16 clocks Set the lock condition of the PLL 4 clocks Set the minimum number of consecutive edges of 16 clocks #default detector output cycles, without appearance of any 64 clocks condition. 256 clocks Set mode of modulation control: external modulation control Modulation will be set via pin ASK/FSK. Description Feedback divider ratio in TX operation mode NT ERTM [18:17] clocks (UP & LDTM [20:19] phase unlock #default MODCTRL [21] 1 internal modulation control Modulation will be set via bit MODSEL (bit 19 in A-word). Nevertheless pin ASK/FSK must be connected to either VCC or VEE. 39010 071221 Rev. 005 Page 25 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 6 6.1 Technical Data Absolute Maximum Ratings Operation beyond absolute maximum ratings may cause permanent damage of the device. Parameter Supply voltage Input voltage Input RF level Storage temperature Junction temperature Power dissipation Thermal Resistance Electrostatic discharge Electrostatic discharge Symbol VCC VIN PiRF TSTG TJ Pdiss RthJA VESD1 VESD2 Condition / Note Min -0.3 -0.3 @ LNA input -40 Max 6.0 Vcc+0.3 10 +125 +150 0.25 60 +1.0 +0.75 Unit V V dBm C C W K/W kV kV human body model, 1) human body model, 2) -1.0 -0.75 1) all pins, except LF, TNK_LO, VCC_PLL and FS1/LD 2) pins LF, TNK_LO, VCC_PLL and FS1/LD 6.2 Normal Operating Conditions Parameter Symbol VCC TA VIL VIL_FS1/LD only in Stand-alone user mode VIH_FS1/LD only in Stand-alone user mode Condition Min 2.2 -40 Max 5.5 +85 0.3*VCC Unit V C V Supply voltage Operating temperature Input low voltage (CMOS) pins IN_DTA, ASK/FSK, RE/SCLK, TE/SDTA, FS0/SDEN, FS1/LD Input high voltage (CMOS) pins IN_DTA, ASK/FSK, RE/SCLK, TE/SDTA, FS0/SDEN, FS1/LD Transmit frequency range Receive frequency range VCO frequency IF range FSK demodulator operating range RO frequency PFD comparison frequency Frequency deviation FSK data rate ASK data rate FM bandwidth VCO gain fRF= 433.92MHz fRF= 868.3MHz VIH fTX fRX fVCO fIF fIF_FSK fRO fR f RFSK RASK fm KVCO 0.7*VCC 300 300 300 0.4 2 3 0.003 2.5 930 930 930 22 22 12 1 80 20 115 40 10 23 55 V MHz MHz MHz MHz MHz MHz MHz kHz kbps kbps kbps kHz MHz/V Set by tank configuration | fRX - fVCO | Set by crystal Set by crystal and R-counter at FM or FSK w/ crystal pulling, NRZ w/ direct VCO mod., NRZ NRZ 14 28 39010 071221 Rev. 005 Page 26 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 6.3 DC Characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at TA = 23 C and VCC = 3 V Parameter Operating currents Standby current Reg. BAND Idle mode (RO only), Reg. IDLESEL = 0 Idle mode, (whole PLL), Reg. IDLESEL = 1 ASK Receive mode, LNA @ low gain ASK Receive mode, LNA @ high gain FSK Receive mode, LNA @ low gain FSK Receive mode, LNA @ high gain Transmit mode, Reg. TXPOWER =00, VPS_PA = 0.3V, continuous wave (CW) mode Transmit mode, Reg. TXPOWER =01, VPS_PA = 0.3V, CW mode Transmit mode, Reg. TXPOWER =10, VPS_PA = 0.3V, CW mode Transmit mode, Reg. TXPOWER =11, VPS_PA = 0.3V, CW mode VIL_FS1/LD only in Stand-alone user mode VIH_FS1/LD only in Stand-alone user mode 0.2 2.3 3.9 2.9 5.3 3.1 5.5 4.0 5.5 4.2 5.7 8.7 11.5 10.0 12.8 11.6 14.4 13.4 16.2 0.3 3.5 6.3 6.1 8.9 7.4 10.2 6.7 9.5 8.0 10.8 13.2 17.1 15.2 19.1 18.6 22.5 23.0 26.9 0.6 4.8 8.0 8.2 12.1 10.3 14.2 9.2 12.9 11.3 15.0 15.6 mA 20.5 18.8 mA 23.7 23.9 mA 28.8 33.2 mA 38.1 mA mA mA mA mA mA ISBY Standby mode 50 200 nA Symbol Condition Min Typ Max Unit Idle current 1 (> 500 MHz) 1 (> 500 MHz) 0 (< 500 MHz) 1 (> 500 MHz) 0 (< 500 MHz) 1 (> 500 MHz) 0 (< 500 MHz) 1 (> 500 MHz) 0 (< 500 MHz) 1 (> 500 MHz) 0 (< 500 MHz) IIDLE Receive supply current - ASK IRXL_ASK IRXH_ASK IRXL_FSK IRXH_FSK Receive supply current - FSK Transmit supply current @ P1 Transmit supply current @ P2 Transmit supply current @ P3 Transmit supply current @ P4 IP1 1 (> 500 MHz) 0 (< 500 MHz) IP2 1 (> 500 MHz) 0 (< 500 MHz) IP3 1 (> 500 MHz) 0 (< 500 MHz) IP4 1 (> 500 MHz) Digital pin characteristics Input low voltage (CMOS) pins IN_DTA, ASK/FSK, VIL RE/SCLK, TE/SDTA, FS0/SDEN, FS1/LD Input high voltage (CMOS) pins IN_DTA, ASK/FSK, VIH RE/SCLK, TE/SDTA, FS0/SDEN, FS1/LD -0.3 0.3*VCC V 0.7*VCC Vcc+0.3 V 39010 071221 Rev. 005 Page 27 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver Parameter Digital pin characteristics Symbol Condition Min Typ Max Unit Pull-down Resistor RPD pins IN_DTA , RE/SCLK, TE/SDTA Low level input leakage current pins IN_DTA, ASK/FSK, IIL RE/SCLK, TE/SDTA, FS0/SDEN, FS1/LD High level input leakage current IIH pins ASK/FSK, FS0/SDEN, FS1/LD Analog pin characteristics MOS switch On resistance FSK_SW pin 70 IINL_FS1/LD only in Stand-alone user mode IINH_FS1/LD only in Stand-alone user mode Transmit mode, if Reg. DTAPOL = 0: IN_DTA = 0 if Reg. DTAPOL = 1: IN_DTA = 1 Transmit mode, if Reg. DTAPOL = 0: IN_DTA = 1 if Reg. DTAPOL = 1: IN_DTA = 0 ASK Receive mode, Reg. PKDET = 1 VOUT_DEM > VINT2/PDO ASK Receive mode, Reg. PKDET = 1 VOUT_DEM =< VINT2/PDO Receive mode Receive mode, Reg. LNACTRL = 0, Reg. LNAHYST = 1 Receive mode, Reg. LNACTRL = 0, Reg. LNAHYST = 1 Receive mode, VIN_IFA = 100V (CW, 10.7MHz) Receive mode, VIN_IFA = 100mV (CW, 10.7MHz) 120 220 k -2 A 2 A RON 10 30 M MOS switch Off resistance FSK_SW pin ROFF 1 M Peak detector pull-up current INT2/PDO pin Peak detector leakage current INT2/PDO pin OA input offset voltage Voltage threshold for high to low LNA gain transition GAIN_LNA pin Voltage threshold for low to high LNA gain transition GAIN_LNA pin RSSI characteristics RSSI voltage at low IFA input level RSSI voltage at high IFA input level IPU_PDO -1.1 mA IL_PDO VOS VGAIN_HL -2 -25 1.0 1.3 2 25 1.6 A mV V VGAIN_LH 1.3 1.6 1.9 V VL_RSSI 0.95 V VH_RSSI 1.95 V 39010 071221 Rev. 005 Page 28 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 6.4 PLL Synthesizer Timings Parameter Channel switching time wide band narrow band Symbol tSW_WB tSW_NB tTX_RX Condition BPLL = 20kHz, ICP = 260A BPLL = 2kHz, ICP = 260A IF = 10.7MHz Min Typ 200 500 1 Max Unit s s ms TX - RX switching time 6.5 AC Characteristics of the Receiver Part all parameters under normal operating conditions, unless otherwise stated; all parameters based on test circuits for FSK (Fig. 14 to 15) and ASK (Fig. 16 to 17), respectively; Parameter fRF= 433.92MHz Input sensitivity ASK fRF= 868.3MHz fRF= 433.92MHz fRF= 868.3MHz fRF= 433.92MHz PminL_FSK Input sensitivity FSK fRF= 868.3MHz fRF= 433.92MHz PminH_FSK fRF= 868.3MHz fRF= 433.92MHz Maximum input signal ASK fRF= 868.3MHz fRF= 433.92MHz fRF= 868.3MHz fRF= 433.92MHz Maximum input signal FSK fRF= 868.3MHz fRF= 433.92MHz fRF= 868.3MHz Start-up time - ASK Start-up time - FSK Spurious emission PmaxL_ASK Symbol PminL_ASK Condition BIF = 150kHz, fm = 2kHz BER 310-3 LNA @ low gain BIF = 150kHz, fm = 2kHz BER 310-3 LNA @ high gain BIF = 150kHz, fm = 2kHz f = 50 kHz BER 310-3 LNA @ low gain BIF = 150kHz, fm = 2kHz f = 50 kHz BER 310-3 LNA @ high gain LNA @ low gain Min Typ -96 -96 -107 -107 -87 dBm -87 -105 dBm -105 -10 -10 -20 -20 -10 -10 -20 -20 1 1 -54 1.5 1.5 dBm Max Unit dBm PminH_ASK dBm PmaxH_ASK LNA @ high gain dBm PmaxL_FSK LNA @ low gain dBm PmaxH_FSK LNA @ high gain ton_ASK ton_FSK Pspur_RX from standby to receive mode from standby to receive mode referred to receiver input dBm ms ms dBm 39010 071221 Rev. 005 Page 29 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 6.6 AC Characteristics of the Transmitter Part all parameters under normal operating conditions, unless otherwise stated; typical values at Ta = 23 C and VCC = 3 V; all parameters based on test circuits for FSK (Fig. 14 to 15) and ASK (Fig. 16 to 17), respectively; Parameter Output power fRF= 433.92MHz fRF= 868.3MHz Output power fRF= 433.92MHz fRF= 868.3MHz Output power fRF= 433.92MHz fRF= 868.3MHz Output power fRF= 433.92MHz fRF= 868.3MHz FSK deviation FM deviation Modulation frequency FM PLL reference spurious emission Harmonic emission Start-up time Symbol P1 Condition mode = transmit, RPS = see para. 7.3 TXPOWER = 00 mode = transmit, RPS = see para. 7.3 TXPOWER = 01 mode = transmit, RPS = see para. 7.3 TXPOWER = 10 mode = transmit, RPS = see para. 7.3 TXPOWER = 11 depends on Cx1, Cx2 and crystal parameters please refer to the FM circuit in the cookbook Min Typ -7 -10 1 -2 6 3 10 9 2.5 25 6 10 -40 -36 From standby to transmit mode 1 1.5 80 Max Unit dBm P2 dBm P3 dBm P4 fFSK fFM fmod Pspur_PLL Pharm ton_TX dBm kHz kHz kHz dBm dBm ms 6.7 Serial Control Interface Parameter Symbol tCS tCH tCWL tCWH tES tEW tEH Condition Min 150 50 100 100 100 100 100 Max Unit ns ns ns ns ns ns ns SDTA to SCLK set up time SCLK to SDTA hold time SCLK pulse width low SCLK pulse width high SCLK to SDEN set up time SDEN pulse width SDEN to SCLK hold time 6.8 Crystal Parameters Parameter Symbol fcrystal Cload C0 R1 aspur Condition fundamental mode, AT Min 3 10 Max 12 15 5 180 -10 Unit MHz pF pF dB Crystal frequency Load capacitance Static capacitance Equivalent series resistance Spurious response only required for FSK 39010 071221 Rev. 005 Page 30 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 7 7.1 Application Circuit Examples FSK Application Circuit Programmable User Mode (internal AFC option) CF2 RX_IN TX_OUT CF1 RF CB6 Lock detect FS0/SDEN 17 CB2 RPS LTX0 CTX4 24 LF 23 C0 L0 VEE_PLL 22 TNK_LO 21 VCC_PLL 20 FS1/LD 19 VEE_DIG 18 CTX0 Combining network 25 OUT_PA 26 IN_LNA SDEN 16 SDTA SCLK CB7 3wire bus RE/SCLK 15 VCC_DIG 14 CRX0 C2 L1 C1 27 VEE_LNA 28 OUT_LNA 29 GAIN_LNA 30 IN_MIX 31 VEE_IF OUT_DEM INT2/PDO TH71221 32L QFN 5x5 ASK/FSK 13 IN_DTA 12 FSK_SW 11 RO 10 OUT_DTA CX2 FSK input IN_DEM VCC_IF INIFA CERFIL CB1 RB1 RSSI INT1 32 OUT_MIX 9 VEE_RO XTAL CX1 1 2 3 4 5 6 7 8 CB5 C3 RSSI FSK output C4 C5 CB0 VCC CERDIS CB4 RP Fig. 14: Test circuit for FSK operation in Programmable User Mode (internal AFC option) 39010 071221 Rev. 005 Page 31 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 7.2 FSK Application Circuit Stand-alone User Mode CF2 RX_IN TX_OUT CF1 RF CB6 see para. 4.1.1 CB2 RPS LTX0 CTX4 24 LF 23 C0 FS0/SDEN 17 L0 VEE_PLL 22 TNK_LO 21 VCC_PLL 20 FS1/LD 19 VEE_DIG 18 CTX0 Combining network 25 OUT_PA 26 IN_LNA 16 RE/SCLK 15 VCC_DIG 14 TX enable CRX0 C2 L1 C1 27 VEE_LNA 28 OUT_LNA 29 GAIN_LNA 30 IN_MIX 31 VEE_IF OUT_DEM INT2/PDO CB7 RX enable TH71221 32L QFN 5x5 ASK/FSK 13 IN_DTA 12 FSK_SW 11 RO 10 OUT_DTA CX2 FSK input IN_DEM VCC_IF INIFA CERFIL CB1 RB1 RSSI INT1 32 OUT_MIX 9 VEE_RO XTAL CX1 1 2 3 4 5 6 7 8 CB5 C3 RSSI FSK output C4 C5 CB0 VCC CERDIS CB4 RP Fig. 15: Test circuit for FSK operation in Stand-alone User Mode 39010 071221 Rev. 005 Page 32 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 7.3 FSK Test Circuit Component List (Fig. 14 and Fig. 15) Size 0603 0603 0603 0603 0603 0805 1210 0603 0603 0603 0603 0603 0603 0603 0603 0805 0805 0603 0603 0603 0603 0603 0603 0603 Part C0 C1 C2 C3 C4 C5 CB0 CB1 CB2 CB4 CB5 CB6 CB7 CF1 CF2 CX1 CX2 CRX0 CTX0 CTX4 RB1 RF RPS L0 Value @ Value @ Value @ 315 MHz 433.92 MHz 868.3 MHz NIP 3.9 pF 1.5 pF 10 nF 330 pF 1.5 nF 10 F 10 nF 330 pF 10 nF 100 nF 100 pF 100 nF 1 nF 100 pF 10 pF 150 pF 100 pF 6.8 pF 12 pF 100 33 k 18 k 68 nH NIP 4.7 pF 1.0 pF 10 nF 330 pF 1.5 nF 10 F 10 nF 330 pF 10 nF 100 nF 100 pF 100 nF 1 nF 68 pF 12 pF 56 pF 100 pF 6.8 pF 5.6 pF 100 33 k 33 k 33 nH NIP 2.7 pF 1.5 pF 10 nF 330 pF 1.5 nF 10 F 10 nF 330 pF 10 nF 100 nF 100 pF 100 nF 1 nF 150 pF 15 pF 18 pF 100 pF 6.8 pF 3.3 pF 100 33 k 39 k 5.6 nH Value @ 915 MHz NIP 1.5 pF 1.5 pF 10 nF 330 pF 1.5 nF 10 F 10 nF 330 pF 10 nF 100 nF 100 pF 100 nF 1 nF 82 pF 12 pF 15 pF 100 pF 6.8 pF 3.3 pF 100 33 k 39 k 4.7 nH Tol. 5% Description VCO tank capacitor LNA output tank capacitor MIX input matching capacitor 5% 5% 10% data slicer capacitor 5% demodulator output low-pass capacitor, depending on data rate 10% RSSI output low pass capacitor 20% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% loop filter capacitor 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% loop filter capacitor RO capacitor for FSK (f = 20 kHz) RO capacitor for FSK (f = 20 kHz) RX coupling capacitor TX coupling capacitor TX impedance matching capacitor protection resistor loop filter resistor power-select resistor VCO tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part LNA output tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part impedance matching inductor from Wurth-Elektronik (WE-KI series) or equivalent part fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 70 ceramic filter from Murata, or equivalent part ceramic Discriminator from Murata, or equivalent part L1 0603 33 nH 15 nH 4.7 nH 4.7 nH 5% LTX0 0603 HC49 SMD 7x5 SMD 3.45x3.1 SMD 4.5x2 15 nH 15 nH 4.7 nH 3.9 nH 5% XTAL CERFIL CERDIS 7.1505 MHz 20ppm cal., 20ppm temp. SFECF10M7HA00 B3dB = 180 kHz CDSCB10M7GA136 Note: - NIP - not in place, may be used optionally - Antenna matching network according to paragraph 9 39010 071221 Rev. 005 Page 33 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 7.4 ASK Application Circuit Programmable User Mode (normal data slicer option) CF2 RPS RX_IN TX_OUT CF1 RF C0 CB6 Lock detect FS0/SDEN 17 CB2 LTX0 CPS CTX4 VEE_PLL 22 24 LF 23 L0 TNK_LO 21 VCC_PLL 20 FS1/LD 19 VEE_DIG 18 CTX0 Combining network 25 OUT_PA 26 IN_LNA SDEN 16 SDTA SCLK CB7 3wire bus RE/SCLK 15 VCC_DIG 14 CRX0 C2 L1 C1 27 VEE_LNA 28 OUT_LNA 29 GAIN_LNA 30 IN_MIX 31 VEE_IF OUT_DEM INT2/PDO TH71221 32L QFN 5x5 ASK/FSK 13 IN_DTA 12 FSK_SW 11 RO 10 OUT_DTA ASK input IN_DEM VCC_IF INIFA CERFIL CB1 RB1 RSSI INT1 32 OUT_MIX 9 VEE_RO XTAL CX1 1 2 3 4 5 6 7 8 CB5 C3 C5 RSSI ASK output CB0 VCC Fig. 16: Test circuit for ASK operation in Programmable User Mode (normal data slicer option) Software Settings for ASK Channel frequency 315.00 MHz 434.00 MHz 915.00 MHz fRO = 8.0000MHz RR 80 80 80 NR 3043 4233 9043 RT 8 8 8 NT 315 434 915 CPCUR RX 260A 260A 260A TX 1300A 1300A 1300A VCOCUR RX 300 A 300 A 300 A TX 900A 900A 900A 39010 071221 Rev. 005 Page 34 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 7.5 ASK Test Circuit Component List (Fig. 16) Size 0603 0603 0603 0603 0603 1210 0603 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0603 0603 0603 Part C0 C1 C2 C3 C5 CB0 CB1 CB2 CB5 CB6 CB7 CF1 CF2 CPS CX1 CRX0 CTX0 CTX4 RB1 RF RPS L0 Value @ 315 MHz 1.0 pF 3.9 pF 1.5 pF 10 nF 1.5 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 100 pF 6.8 pF 12 pF 100 33 k 18 k 56 nH Value @ 434 MHz 2.2 pF 5.6 pF 1.0 pF 10 nF 1.5 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 100 pF 6.8 pF 5.6 pF 100 33 k 33 k 22 nH Value @ 915 MHz 3.3 pF 1.5 pF 1.5 pF 10 nF 1.5 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 10 pF 6.8 pF 3.3 pF 100 33 k 43 k 3.3 nH Tol. 5% 5% 5% 10% 10% 20% 10% 10% 10% 10% 10% 10% 5% 10% 5% 5% 5% 5% 5% 5% 5% 5% Description VCO tank capacitor LNA output tank capacitor MIX input matching capacitor data slicer capacitor RSSI output low pass capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor loop filter capacitor loop filter capacitor power-select capacitor RO capacitor RX coupling capacitor TX coupling capacitor TX impedance matching capacitor protection resistor loop filter resistor power-select resistor VCO tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part LNA output tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part impedance matching inductor from Wurth-Elektronik (WE-KI series) or equivalent part fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 70 ceramic filter from Murata, or equivalent part L1 0603 33 nH 15 nH 4.7 nH 5% LTX0 0603 HC49 SMD 7x5 SMD 3.45x3.1 15 nH 15 nH 3.9 nH 5% XTAL CERFIL 8.0000 MHz 20ppm cal., 20ppm temp. SFECF10M7HA00 B3dB = 180 kHz Note: - Antenna matching network according to paragraph 9 39010 071221 Rev. 005 Page 35 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 7.6 ASK Application Circuit Programmable User Mode (peak detector option) CF2 RPS RX_IN TX_OUT CF1 RF C0 CB6 Lock detect FS0/SDEN 17 CB2 LTX0 CPS CTX4 VEE_PLL 22 24 LF 23 L0 TNK_LO 21 VCC_PLL 20 FS1/LD 19 VEE_DIG 18 CTX0 Combining network 25 OUT_PA 26 IN_LNA SDEN 16 SDTA SCLK CB7 3wire bus RE/SCLK 15 VCC_DIG 14 CRX0 C2 L1 C1 27 VEE_LNA 28 OUT_LNA 29 GAIN_LNA 30 IN_MIX 31 VEE_IF OUT_DEM INT2/PDO TH71221 32L QFN 5x5 ASK/FSK 13 IN_DTA 12 FSK_SW 11 RO 10 OUT_DTA ASK input IN_DEM VCC_IF INIFA CERFIL CB1 RB1 RSSI INT1 32 OUT_MIX 9 VEE_RO XTAL CX1 1 2 3 4 5 6 7 8 CB5 C6 R1 R2 C5 RSSI ASK output CB0 VCC Fig. 17: Test circuit for ASK operation in Programmable User Mode (internal Peak Detector option) Software Settings for ASK Channel frequency 315.00 MHz 434.00 MHz 915.00 MHz fRO = 8.0000MHz RR 80 80 80 NR 3043 4233 9043 RT 8 8 8 NT 315 434 915 CPCUR RX 260A 260A 260A TX 1300A 1300A 1300A VCOCUR RX 300 A 300 A 300 A TX 900A 900A 900A 39010 071221 Rev. 005 Page 36 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 7.7 ASK Test Circuit Component List (Fig. 17) Size 0603 0603 0603 0603 0603 1210 0603 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 Part C0 C1 C2 C5 C6 CB0 CB1 CB2 CB5 CB6 CB7 CF1 CF2 CPS CX1 CRX0 CTX0 CTX4 R1 R2 RB1 RF RPS L0 Value @ 315 MHz 1.0 pF 3.9 pF 1.5 pF 1.5 nF 100 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 100 pF 6.8 pF 12 pF 100 k 680 k 100 33 k 18 k 56 nH Value @ 434 MHz 2.2 pF 5.6 pF 1.0 pF 1.5 nF 100 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 100 pF 6.8 pF 5.6 pF 100 k 680 k 100 33 k 33 k 22 nH Value @ 915 MHz 3.3 pF 1.5 pF 1.5 pF 1.5 nF 100 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 10 pF 6.8 pF 3.3 pF 100 k 680 k 100 33 k 43 k 3.3 nH Tol. 5% 5% 5% 10% 10% 20% 10% 10% 10% 10% 10% 10% 5% 10% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% Description VCO tank capacitor LNA output tank capacitor MIX input matching capacitor RSSI output low pass capacitor PKDET capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor loop filter capacitor loop filter capacitor power-select capacitor RO capacitor RX coupling capacitor TX coupling capacitor TX impedance matching capacitor PKDET resistor PKDET resistor protection resistor loop filter resistor power-select resistor VCO tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part LNA output tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part impedance matching inductor from Wurth-Elektronik (WE-KI series) or equivalent part fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 70 ceramic filter from Murata, or equivalent part L1 0603 33 nH 15 nH 4.7 nH 5% LTX0 0603 HC49 SMD 7x5 SMD 3.45x3.1 15 nH 15 nH 3.9 nH 5% XTAL CERFIL 8.0000 MHz 20ppm cal., 20ppm temp. SFECF10M7HA00 B3dB = 180 kHz Note: - Antenna matching network according to paragraph 9 39010 071221 Rev. 005 Page 37 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 8 Extended Frequency Range The operating frequency range of 300 MHz to 930 MHz can be covered without the use of an additional VCO varactor diode. A frequency range extension down to 27 MHz can be realized by adding an external varactor diode to the VCO tank. VCC RF RX_IN TX_OUT R01 C01 VD1 C0 RB0 CB6 Lock detect FS0/SDEN 17 RPS CF2 CF1 CB2 RF1 VEE_PLL 22 TNK_LO 21 LTX0 L0 VCC_PLL 20 FS1/LD 19 VEE_DIG 18 CTX4 24 LF 23 CTX0 Combining network 25 SDEN 16 SDTA SCLK CB7 OUT_PA 3wire bus 26 IN_LNA RE/SCLK 15 CRX0 27 VEE_LNA 28 OUT_LNA 29 GAIN_LNA TH71221 TH71121 VCC_DIG 14 ASK/FSK 13 IN_DTA Fig. 18: VCO tank circuit for extended frequency range VCC 8.1 Part C0 C01 CB2 VD1 CF1 CF2 CTX4 RB0 R01 RF RF1 RPS CTX0 CRX0 L0 LTX0 CB6 CB7 Board Component List (Fig. 18) Size 0805 0805 0603 SOD-323 0605 0605 0605 0605 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 Value @ 27 MHz NIP 1 nF 330 pF BBY65 1 F 220 nF NIP 100 22 1.8 k 10 k 15 k 10 nF 10 nF 1.2 H 2.2 H 10 nF 100 nF Value @ 40 MHz NIP 1 nF 330 pF BBY65 1 F 100 nF 33 pF 100 22 1.8 k 10 k 15 k 10 nF 10 nF 1.0 H 330 nH 10 nF 100 nF Value @ 80 MHz NIP 68 pF 330 pF BB639 1F 100nF 18pF 100 0 1.8 k 10 k 15 k 10 nF 10 nF 220 nH 220 nH 10 nF 100 nF Value @ 144 MHz NIP 100pF 330 pF BB833 1F 100 nF 10 pF 100 0 2.7 k 10 k 22 k 1 nF 1 nF 100 nH 100 nH 1 nF 100 nF Value @ 170 MHz NIP 100 pF 330 pF BB535 1F 100 nF 8.2 pF 100 0 390 10 k 33 k 220 pF 220 pF 47 nH 100 nH 1 nF 100 nF Description VCO tank capacitor VCO tank capacitor de-coupling capacitor varactor diode loop filter capacitor loop filter capacitor TX impedance matching capacitor protection resistor VCO tank resistor loop filter resistor loop filter resistor power-select resistor TX coupling capacitor RX coupling capacitor VCO tank inductor TX impedance matching inductor de-coupling capacitor de-coupling capacitor fR NT NR LO injection 25 kHz 1080 1508 high 25 kHz 1600 2028 high 25 kHz 3200 2772 low 25 kHz 5760 5332 low 100 kHz 1700 1807 high frequency resolution NT counter NR counter Note: The component values are optimized for the above listed settings of fR, NR and NT. Direct VCO modulation as explained in section 3.3.5 must be applied. 39010 071221 Rev. 005 Page 38 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 9 9.1 Part CRX0 CTX0 CTX1 CTX2 CTX4 LRX2 LTX0 LTX1 CB2 TX/RX Combining Network Board Component List (Fig. 19) Size 0603 0603 0603 0603 0603 0603 0603 0603 0603 Value @ Value @ Value @ Value @ 315 433.92 868.3 915 MHz MHz MHz MHz 100 pF 6.8 pF 10 pF 10 pF 12 pF 82 nH 15 nH 33 nH 330 pF 100 pF 6.8 pF 6.8 pF 6.8 pF 5.6 pF 56 nH 15 nH 33 nH 330 pF 100 pF 6.8 pF 4.7 pF 4.7 pF 3.3 pF 10 nH 4.7 pF 8.2 nH 330 pF 100 pF 6.8 pF 3.9 pF 3.9 pF 3.3 pF 6.8 nH 3.9 nH 8.2 nH 330 pF " " No TX/RX switch required Direct connection to /4 antenna possible CB2 VCC RF input RF output LTX0 LTX1 CTX4 50 CTX2 CTX1 CTX0 LRX2 25 OUT_PA 26 IN_LNA CRX0 Fig. 19: Combining network schematic 9.2 Typical LNA S-Parameters in Receive Mode Low Gain Mode Frequency 27 MHZ 40 MHz 80 MHz 170 MHz 315 MHz 433 MHz 868 MHz 915 MHz Note: Re[S11] 0.9138 0.9139 0.9126 0.9054 0.8836 0.8622 0.7161 0.6975 Im[S11] -0.0145 -0.0229 -0.0481 -0.1026 -0.1814 -0.2625 -0.4577 -0.4753 Re[S12] 6.06E-005 5.53E-005 5.36E-005 7.44E-004 2.16E-004 7.81E-004 2.35E-003 2.24E-003 Im[S12] 4.27E-004 6.73E-004 1.48E-004 3.25E-003 6.21-E003 6.34E-003 1.09E-003 1.10E-003 Re[S21] -0.4172 -0.4092 -0.3989 -0.3828 -0.3300 -0.3248 -0.1265 -0.1062 Im[S21] 0.0334 0.0400 0.0581 0.1056 0.1798 0.2168 0.3187 0.3206 Re[S22] 0.9986 0.9984 0.9979 0.9966 0.9926 0.9870 0.9543 0.9494 Im[S22] -0.0095 -0.0136 -0.0265 -0.0558 -0.1033 -0.1417 -0.2829 -0.2980 input and output of the LNA are connected to 50 ports without matching elements High Gain Mode Frequency 27 MHZ 40 MHz 80 MHz 170 MHz 315 MHz 433 MHz 868 MHz 915 MHz Note: Re[S11] 0.8417 0.8424 0.8403 0.8273 0.7884 0.7492 0.5007 0.4714 Im[S11] -0.0151 -0.0276 -0.0621 -0.1344 -0.2328 -0.3405 -0.5322 -0.5440 Re[S12] 1.36E-004 1.42E-004 1.52E-004 1.86E-004 4.02E-004 1.51E-004 2.36E-004 1.94E-004 Im[S12] 8.63E-005 1.07E-004 1.83E-004 3.72E-003 7.04E-003 6.18E-003 1.06E-003 1.06E-003 Re[S21] -4.0840 -4.0840 -4.0630 -3.9550 -3.5100 -3.4700 -1.6710 -1.4690 Im[S21] 0.1272 0.2055 0.4338 0.9279 1.6990 1.9920 3.2230 3.2700 Re[S22] 0.9994 0.9994 0.9991 0.9977 0.9846 0.9839 0.9501 0.9451 Im[S22] -0.0092 -0.0135 -0.0269 -0.0571 -0.1072 -0.1439 -0.2847 -0.2995 input and output of the LNA are connected to 50 ports without matching elements 39010 071221 Rev. 005 Page 39 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 9.3 LNA Input Impedances in Transmit Mode LNA off, Pin LNA is shorted RS 33.6 33.6 33.6 34.3 LS 1.9 nH 2.1 nH 2.4 nH 2.2 nH Frequency 315 MHz 433 MHz 868 MHz 915 MHz RS 32.7 33.6 35.7 36.6 LS 2.2 nH 2.3 nH 2.7 nH 2.8 nH IN_LNA 26 Mode Frequency 27 MHz 40 MHz 80 MHz 170 MHz RS LS 39010 071221 Rev. 005 Page 40 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 10 Package Description The device TH71221 is RoHS compliant. D 24 25 17 16 A3 E 32 1 e 8 b 9 A1 A exp osed pad E2 L D2 The "exposed pad" is not connected to internal ground, it should not be connected to the PCB. Fig 12: all Dimension in mm D min max min max 4.75 5.25 0.187 0.207 32L QFN 5x5 Quad E 4.75 5.25 0.187 0.207 D2 3.00 3.25 0.118 0.128 E2 3.00 3.25 0.118 0.128 A 0.80 1.00 0.0315 0.0393 A1 0 0.05 0 0.002 A3 0.20 L 0.3 0.5 0.0118 0.0197 e 0.50 b 0.18 0.30 0.0071 0.0118 all Dimension in inch 0.0079 0.0197 10.1 Soldering Information * The device TH71221 is qualified for MSL3 with soldering peak temperature 260 deg C according to JEDEC J-STD-20 39010 071221 Rev. 005 Page 41 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 11 Reliability Information This Melexis device is classified and qualified regarding soldering technology, solderability and moisture sensitivity level, as defined in this specification, according to following test methods: Reflow Soldering SMD's (Surface Mount Devices) * * IPC/JEDEC J-STD-020 "Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2)" EIA/JEDEC JESD22-A113 "Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2)" Wave Soldering SMD's (Surface Mount Devices) and THD's (Through Hole Devices) * * EN60749-20 "Resistance of plastic- encapsulated SMD's to combined effect of moisture and soldering heat" EIA/JEDEC JESD22-B106 and EN60749-15 "Resistance to soldering temperature for through-hole mounted devices" Iron Soldering THD's (Through Hole Devices) * EN60749-15 "Resistance to soldering temperature for through-hole mounted devices" Solderability SMD's (Surface Mount Devices) and THD's (Through Hole Devices) * EIA/JEDEC JESD22-B102 and EN60749-21 "Solderability" For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD's is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of the Use of Certain Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality_leadfree.aspx 12 ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 39010 071221 Rev. 005 Page 42 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver Your Notes 39010 071221 Rev. 005 Page 43 of 44 Data Sheet June/07 TH71221 27 to 930MHz FSK/FM/ASK Transceiver 13 Disclaimer 1) The information included in this documentation is subject to Melexis intellectual and other property rights. Reproduction of information is permissible only if the information will not be altered and is accompanied by all associated conditions, limitations and notices. 2) Any use of the documentation without the prior written consent of Melexis other than the one set forth in clause 1 is an unfair and deceptive business practice. Melexis is not responsible or liable for such altered documentation. 3) The information furnished by Melexis in this documentation is provided 'as is'. Except as expressly warranted in any other applicable license agreement, Melexis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merchantability, fitness for a particular purpose, title and non-infringement with regard to the content of this documentation. 4) Notwithstanding the fact that Melexis endeavors to take care of the concept and content of this documentation, it may include technical or factual inaccuracies or typographical errors. Melexis disclaims any responsibility in connection herewith. 5) Melexis reserves the right to change the documentation, the specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. 6) Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the information in this documentation. 7) The product described in this documentation is intended for use in normal commercial applications. Applications requiring operation beyond ranges specified in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. 8) Any supply of products by Melexis will be governed by the Melexis Terms of Sale, published on www.melexis.com. (c) Melexis NV. All rights reserved. For the latest version of this document, go to our website at: www.melexis.com Or for additional information contact Melexis Direct: Europe, Africa: Phone: +32 1367 0495 E-mail: sales_europe@melexis.com Americas: Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com Asia: Phone: +32 1367 0495 E-mail: sales_asia@melexis.com ISO/TS 16949 and ISO14001 Certified 39010 071221 Rev. 005 Page 44 of 44 Data Sheet June/07 |
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